Eliyan connects AI chiplets, memory and optical modules

AI hardware is constrained by where data can move, not only by how quickly a processor can calculate. Memory, compute dies and network interfaces must share a limited amount of package space, electrical power and connection area. Eliyan develops interconnect intellectual property and chiplets aimed at these constraints. Its portfolio spans short electrical connections within a package, links between packages and a newly announced optical platform. A useful evaluation starts by identifying which of those boundaries is actually limiting the design.

01 / ProductElectrical IP and optical chiplets serve different boundaries

The product catalog separates NuLink die-to-die IP from the NuLink-XS chip-to-chip IP family, underpinned by NuLink-X technology. NuLink-SP targets standard organic packaging, while NuLink-AP targets advanced packaging. These are physical interface building blocks incorporated into a silicon design. They should not be confused with an accelerator board that an application developer can install or a memory upgrade for an arbitrary existing server.

The technology description discusses UCIe and Bunch of Wires compatibility, alongside proprietary signaling and memory-interface approaches. Protocol support and physical implementation are distinct. An interface may move bits efficiently while the surrounding controllers still determine coherency, error handling and access semantics. For a buyer, the important artifact is the exact supported configuration and integration specification, rather than the broad claim that an interface is protocol-agnostic.

NuLight addresses another distance scale. Eliyan's October 2026 announcement introduces Nexus and Oscar chiplets and says both are sampling. Nexus bridges high-speed electrical traffic toward parallel optical lanes; Oscar provides electrical interfaces to optical arrays. The announced platform targets module makers and future AI fabrics. Sampling is a concrete availability stage, but it does not mean every planned optical module is already qualified for volume deployment.

02 / AudienceThe reader needs control over the hardware design

Eliyan is relevant when a chip team can choose the interface and packaging strategy before tape-out. One potential customer has a compute architecture that needs more memory connections than the package edge comfortably supports. Another wants to move an I/O function away from expensive compute silicon. A third builds optical modules and needs a bridge between a host interface and its chosen optical technology. Each buys a different integration project.

The markets page identifies AI, high-performance computing and other chiplet applications. That breadth does not establish that one PHY configuration works across all environments. An industrial product with a long service life and a hyperscale accelerator with aggressive bandwidth targets may place very different demands on package qualification, repair and component availability. Define the operating environment before selecting a headline bandwidth figure.

For an application team buying completed compute, suppliers such as AMD sit closer to the immediate decision. Astera Labs is an adjacent connectivity comparison at different system interfaces. These distinctions help avoid a category error: Eliyan can matter enormously to the platform underneath an AI service while being too early in the manufacturing chain for that service's developer to purchase directly.

03 / WorkflowProposed workflow for a memory-constrained accelerator

Imagine a proposed inference ASIC whose arithmetic units repeatedly wait for weights or intermediate data. Start by profiling the memory demand of representative model shapes and batch sizes. Record sustained bandwidth, capacity needs and the time spent waiting on transfers. A larger theoretical interface will not help if the workload is limited by another dependency, or if software cannot issue enough concurrent requests to keep that interface busy.

Build alternative package floorplans with realistic compute, memory and I/O placement. In one, retain the established memory interface and packaging approach. In another, explore an Eliyan-supported configuration with the appropriate companion components. Compare routing distance, bump allocation, thermal density and the area consumed by interfaces. The purpose is to discover whether the new connection changes a practical placement limit, not to maximize an isolated bandwidth-density number.

Then model read-heavy and write-heavy traffic separately. Memory connections often change direction, while an accelerator fabric may need simultaneous traffic in both directions. The signaling mode, controllers and protocol must match the workload. Check whether turnaround, arbitration or buffering erodes the predicted gain. This is a proposed design exercise, not a claim that Sequenced built or measured a NuLink system.

Move to a test vehicle only after the full connection is specified. Verify electrical margin, interoperability and error recovery across the expected voltage and temperature conditions. Include the software path that reports errors to the host. A link that passes a clean laboratory transfer test still needs a defined response to a marginal connection, a failing lane or a reset on one side while the other remains active.

Keep an optical-module investigation separate if the objective is rack-to-rack reach. It requires its own optical budget, connectors, management interfaces and qualification plan. Reusing the same company across these projects may simplify a commercial conversation, but does not make the electrical package proof an optical system proof. The acceptance evidence should remain specific to the boundary being changed.

04 / PricingThe price follows the IP or chiplet configuration

The catalog directs product information and ordering to the contact route. No public numeric license or chiplet tariff was verified. A license to integrate a PHY, a supplied chiplet and the services needed to qualify a package are different commercial items. The public pages do not establish that all three are bundled, or that support for every process node is available on identical terms.

Build the economic comparison around a complete manufactured device. Include integration engineering, test coverage, package yield and the treatment of rejected assemblies. A cheaper substrate can still lose its advantage if the total assembly is harder to test or repair. Conversely, a more expensive interface may be valuable if it removes a larger constraint on usable memory or product configuration. Those conclusions require the customer's own bill of materials and volume assumptions.

05 / DistinctionsThe distinctive choice is where to spend connection area

Eliyan's electrical approach makes the interface between dies a design variable instead of treating it as a fixed boundary. In practical terms, a chip team can ask whether compute, memory and I/O functions belong on one piece of silicon, several dies on a substrate, or separate packages. The resulting freedom is only useful when it improves a system-level requirement such as reachable memory capacity, thermal distribution or manufacturing flexibility.

The optical announcement describes a wide parallel-lane approach and on-the-fly lane repair. Treat these as vendor-described mechanisms to investigate, without assuming a measured reliability advantage in the reader's system. More parallel paths create a different engineering problem from driving fewer paths faster. The appropriate comparison includes spare capacity, diagnostic coverage, assembly tolerance and what happens after the available redundancy is exhausted.

The 2026 financing announcement reports additional investment directed toward electro-optical development and manufacturing. It supports the company's current activity and strategic relevance. Financing is not a substitute for a qualified part, however. A buyer should base readiness on the offered silicon revision and delivery evidence, while treating broader roadmap expansion as a separate consideration.

06 / QuestionsClarify interoperability, readiness and the memory semantics

The first question is what exists in qualified form for the intended process and package. A product family can contain several generations, and a table may combine currently available options with a developing roadmap. Ask for the exact deliverables, verification models, physical constraints and silicon evidence attached to the proposed license. An example integration diagram should not become an assumed production configuration.

The second question is whether the memory architecture remains transparent to software. Adding capacity through a different link can introduce new latency, bandwidth or management characteristics. Determine which component owns memory initialization, fault reporting and recovery. If a system exposes multiple memory tiers, application placement may matter as much as link efficiency. A physical connection alone does not specify a uniform programming model.

The third question concerns optical maturity. The NuLight announcement is explicit about sampling, while its longer-term path includes future co-packaged optics. Keep those stages separate in a product plan. For a near-term deployment, request evidence for the actual module and host combination; for a future design, identify which dependencies remain on the roadmap and preserve an alternative if they do not arrive in time.

07 / DecisionSelect the interconnect for a defined hardware boundary